Non-volatile memory devices include a class of electrically erasable and programmable memory devices that are frequently used in data storage systems. Such data storage systems may utilize error detection and correction (EDC) circuitry to detect and correct a limited number of data errors that occur when programming and reading the non-volatile memory devices, which may have one or more defective memory cells therein. In some applications that do not require very high levels of data integrity, it may not be necessary for the EDC circuitry to correct all detected errors. Nonetheless, it may be necessary that the number of uncorrected errors in the storage system be monitored to insure that the number is not too large for the intended application. One conventional device for detecting bit failures may be utilized in a system containing non-volatile memory devices with single-level memory cells (SLC) and EDC circuitry that can correct one-bit failures. This device is described in Korean Patent Publication No. 2002-43378.
The manufacturing yield of non-volatile memory devices having multiple memory array blocks therein may be increased if efficient testing techniques are utilized to identify and disable defective memory array blocks within the memory device. However, as more advanced non-volatile memory devices are developed using multi-level memory cells (MLC), EDC circuitry will also need to be developed to detect and correct a greater number of errors.